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Processing Instruction
Results: 1077

#	Item
401	Alpha[removed]Microprocessor Data Sheet Order Number: EC–QAEPD–TE Revision/Update Information: Digital Equipment Corporation Add to Reading List Source URL: download.majix.org Language: English - Date: 2013-01-10 05:03:36 Computing DEC Alpha PALcode Control register CPU cache Joint Test Action Group Alpha 21164 Instruction set Translation lookaside buffer Computer architecture Computer hardware Central processing unit
402	RelaxReplay: Record and Replay for Relaxed-Consistency Multiprocessors Nima Honarmand and Josep Torrellas University of Illinois at Urbana-Champaign http://iacoma.cs.uiuc.edu/ Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2014-03-10 10:28:34 Central processing unit Instruction set
403	The RISC-V Instruction Set Manual Volume I: User-Level ISA Version 2.0 Andrew Waterman, Yunsup Lee, David Patterson, Krste Asanovi´c CS Division, EECS Department, University of California, Berkeley Add to Reading List Source URL: riscv.org Language: English - Date: 2014-08-05 19:51:49 Instruction set X86 Microarchitecture Central processing unit ARM architecture Reduced instruction set computing 64-bit Very long instruction word IBM POWER Computer architecture Instruction set architectures DEC Alpha
404	Digital Semiconductor Alpha[removed]and Alpha 21064A Microprocessors Hardware Reference Manual Order Number: EC–Q9ZUC–TE Add to Reading List Source URL: download.majix.org Language: English - Date: 2013-01-10 05:01:58 Computing Alpha 21064 Computer memory DEC Alpha PALcode CPU cache Instruction set Alpha 21164 Computer architecture Computer hardware Central processing unit
405	21264/EV68A Microprocessor Hardware Reference Manual Part Number: DS–0038B–TE This manual is directly derived from the internal[removed]EV68A Specifications, Revision 1.1. You can access this hardware reference manual Add to Reading List Source URL: download.majix.org Language: English - Date: 2013-01-10 05:03:05 Instruction set architectures Computer memory DEC Alpha PALcode Alpha 21264 CPU cache ARM architecture Processor register Instruction set Computer architecture Computer hardware Central processing unit
406	Compiler Writer’s Guide for the[removed]Part Number: EC–0100A–TE This document provides guidance for writing compilers for the[removed]and Add to Reading List Source URL: download.majix.org Language: English - Date: 2013-01-10 05:03:16 Central processing unit Computer memory DEC Alpha Data structure alignment CPU cache Instruction set Floating point Classic RISC pipeline X86 Computer architecture Computing Instruction set architectures
407	Alpha[removed]EV67 Microprocessor Hardware Reference Manual Order Number: DS–0028C–TE This manual is directly derived from the internal[removed]EV67 Specifications, Revision 1.5. You can access this hardware reference m Add to Reading List Source URL: download.majix.org Language: English - Date: 2013-01-10 05:03:51 Computer engineering DEC Alpha Alpha 21264 PALcode CPU cache Processor register Instruction set Computer architecture Computer hardware Central processing unit
408	CAVA: Hiding L2 Misses with Checkpoint-Assisted Value Prediction Luis Ceze, Karin Strauss, James Tuck, Jose Renau† and Josep Torrellas University of Illinois at Urbana-Champaign {luisceze, kstrauss, jtuck, torrellas}@c Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2004-12-21 00:54:20 Central processing unit Runahead CPU cache Microprocessors Branch predictor Memory-level parallelism Microarchitecture Instruction window Hardware scout Computer architecture Computer hardware Computer engineering
409	RelaxReplay: Record and Replay for Relaxed-Consistency Multiprocessors Nima Honarmand and Josep Torrellas University of Illinois at Urbana-Champaign {honarma1,torrella}@illinois.edu http://iacoma.cs.uiuc.edu Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2014-01-10 19:23:01 Computing Parallel computing Instruction set CPU cache Microarchitecture Processor register Linearizability MIMD Computer architecture Computer hardware Central processing unit
410	Prototyping Architectural Support for Program Rollback Using FPGAs ∗ Radu Teodorescu and Josep Torrellas Department of Computer Science University of Illinois at Urbana-Champaign {teodores,torrellas}@cs.uiuc.edu Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2005-05-11 13:27:29 Computer engineering CPU cache Microarchitecture Speculative execution Processor register Application checkpointing Parallel computing Instruction set Multithreading Computer architecture Computer hardware Central processing unit

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